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fedl7066-01 issue date: april. 28, 2011 ML7066 400mhz transceiver ic for specified low-power station 1/29 zigbee ? is a registered trademark of zigbee alliance, inc. other names are trademarks or registered trademarks of developers and manufacturers. the information contained herein can change without notice owing to product and/or technical improvements. general description the ML7066 is an transceiver ic that can be used for specified low-power statiom , where the rf section, if section, modem section and host interface section are integrated into one chip . it supports the 400mhz radio communication and complies with rcr std-30 (426mhz) and arib std-t67 (429mhz). the ML7066 is suitable for auto meter reading, home securithy systems, wireless fire alarm system, and industorial monitoring and control. features ? complies with rcr std-30 (low-power radio security system) and atib std-t67 (specified low-power radio statiion) ? operating frequency 426.0250 mhz to 426.8375 mhz 429.1750 mhz to 429.9250 mhz note: including the frequency range that are not defined in the standards. ? data transfer speed 1200 bps, 2400 bps and 4800 bps with nrz coding 600 bps, 1200 bps and 2400 bps with manchester coding ? 2-fsk modulation ? voltage regulator installed ? 19.2 mhz oscillator circuit installed ? synchronous communication interface (sci) installed ? up to 8 oeration channel set function installed ? carrier (0perating frequency) detect function installed ? up to 16 bytes preamble generator and detecor installed ? up to 18 bytes start-of-frame delimiter generator and detector installed ? intermittent operation function installed (periodic transmition and receiving) ? pll adjustment function availble to use 60ppm crystal ? test pattern generatot installed (cw, pn9, pn15, all ?0?, all?1?) ? power supply voltage 2.1v to 3.6v ? current consumption in the following states (typical); stop mode: 0.7 ua sleep mode: 4 ua idle mode: 2 ma at transmission (@10mw) 29.5 ma at reception: 15.5 ma ? package 48-pin vqfn p-vqfn48-0707-0.50-t6 product name: ML7066gdz0ab ? package lead-free package conforming to rohs
fedl7066-01 ML7066 2/29 block diagram resetn sresetn extclk powoff mode1 mode2 sdin sdo sclk sint scen dio dclk rf_in_n if1_out if1_in rf_in_p rf_out pll_lp pll_bg vreg_out vreg_in lc filter rssi 429mhz 455khz 21.4mhz synthesizer fractional-n pll 1st if 1st mixer 2 n d if lna pa saw filter 429mhz limiter modulator s c i & data i/f mdoem control demodulator control regulator tank1 tank2 sw_ctrl vreg_core (monitor pin) adc if2_out if2_in 19.2mhz vbg if frequency conversion
fedl7066-01 ML7066 3/29 pin configuration 48-pin vqfn v bg v reg _ core v reg _ in v reg_out v dd_pll v dd_cp pll_lp pll_bg v dd_rf_if tank2 tank1 v dd_vco 36 3 5 34 33 3 2 31 3 0 2 9 28 27 2 6 25 regpdoin 37 24 n.c . mode1 38 23 if2_in mode2 39 22 n.c . v ddio 40 21 if2_out sdin 41 20 gnd_rf_if gnd 42 19 if1_in sd o 43 18 v dd _ if sclk 44 17 if1_out scen 45 16 v dd _m i x sint 46 15 rf _ in _ p powoff 47 14 gnd _ rf _ if extclk 48 13 rf_in_n 1 2 3 4 5 67 8 9101112 x o x i gnd dio vddio dcl k sresetn resetn sw _ ctr l vdd_r f gnd _ rf _ if rf_ou t l ower su rfac e of pkg: gn d top view
fedl7066-01 ML7066 4/29 description of pins i/o definition i rf : rf input pin i a : analog input pin i : digital input pin i s : schmitt trigger input pin i u : input pin with pull-up register i d : input pin with pull-down register i os : input pin for 24mhz oscillation circuit o rf : rf control output pin o a : analog output pin o : digital output pin o os : output pin for 24mhz oscillation circuit o d : open drain output pin rf related pins pin no. pin name attribute/ value at reset i/o active level description 12 rf_out o o rf ? rf output pin 13 rf_in_n i i rf ? positive rf input pin (differential) 15 rf_in_p i i rf ? negative rf input pin (differential) 17 if1_out o o a ? 1 st if filter pin (output to filter) 19 if1_in i i a ? 1 st if filter pin (input from filter) 21 if2_out o o a ? 2 nd if filter pin (output to filter) 23 if2_in i i a ? 2 nd if filter pin (input from filter) 29 pll_bg o o a ? loop filter related pin 30 pll_lp o o a ? loop filter pin 26 tank1 i i a ? vco tank inductor pin 1 27 tank2 i i a ? vco tank inductor pin 2 host interface pins pin no. pin name attribute/ value at reset i/o active level description 41 sdin i i h or l synchronous communication interface data input pin 43 sdo l o h or l synchronous communication interface data output pin 44 sclk i i p or n synchronous communication interface clock input pin 46 sintn h o l synchronous communication interface interrupt output pin 45 scen i i u l synchronous communication interface chip select input pin
fedl7066-01 ML7066 5/29 tx/rx data related pins pin no. pin name attribute/ value at reset i/o active level description 4 dio i io h or l data input/output pin (initial value is low when switch the state from input to output) 6 dclk l o p or n data clock output pin regulator related pins pin no. pin name attribute/ value at reset i/o active level description 33 vreg_out ? ? ? power supply output pin for the rf block (typ. 2.2v) do not use this pin for purposes other than rf power supply. 35 vreg_core ? ? ? power supply monitor pin for the core (typ. 2.2v) do not use this pin for purposes other than monitoring purpose. decuple this pin to ground with capacitor. (*1) 36 vbg ? ? ? back bias pin (capacitance connection) decuple this pin to ground with capacitor. (*1) 37 regpdin l i d ? regulator power down pin always fix this pin to ?l? input in normal operation. *1: please refer reference circuit.
fedl7066-01 ML7066 6/29 power supply pins pin no. pin name attribute/ value at reset i/o active level description 34 vreg_in ? ? ? power supply pin for regulator. (typ. 3.0 v) 10 vdd_rf ? ? ? power supply pin for pa and lna. connect to vreg_out. (typ. 2.2v). 25 vdd_vco ? ? ? power supply pin for vco. connect to vreg_out. (typ. 2.2v) 16 vdd_mix ? ? ? power supply pin for mixer 1. connect to vreg_out. (typ. 2.2v) 31 vdd_cp ? ? ? power supply pin for charge pump. connect to vreg_out. (typ. 2.2v) 32 vdd_pll ? ? ? power supply pin for pll. connect to vreg_out. (typ. 2.2v) 18 vdd_if ? ? ? power supply pin for if, limiter and rssi. connect to vreg_out. (typ. 2.2v) 5, 40 vddio ? ? ? power supply pins for the digital i/o block and internal voltage regulator. (typ. 3.0 v). 11, 14 20,28 gnd_rf_if ? ? ? ground pin for rf and if block. 3,42 gnd ? ? ? ground pin for digital block. el (*2) ? ? ? ? ground pin (*2) el is the lower surface of the lsi.
fedl7066-01 ML7066 7/29 other pins pin no. pin name attribute/ value at reset i/o active level description 8 resetn i i s l hardware reset pin 7 sresetn i i u l software reset pin wake up pin when in sleep mode. this pin is active when resetn=1. 2 xi i i os p or n 19.2 mhz crystal connection pin 1 external clock input pin. 1 xo o o os ? 19.2 mhz crystal connection pin 2 leave open when xi (pin #2) is configured as an external clock input pin. 9 sw_ctrl o o d l antenna switch control pin l: in transmitting mode hiz: in receiving mode 47 powoff l o h external component power on/off control pin active level polarity is changeable by register setting. 48 extclk i i p or n external 32.768 khz clock input pin (*3) 38 mode1 i io h or l bit order on sci data setting pin l: lsb first h: msb first 39 mode2 i i h or l operation mode setting pin l: normal mode h: test mode always fix this pin to ?l? input in normal operation. 22,24 nc o o a ? unused. (open) (*3) always extclk input is required for ML7066 operation. recommended handling of unused pins lapis semiconductor recommends handling unused pins as shown below so that the basic operation of the ml7275 is unimpaired. pin no. pin name recommended pin handling 1 xo open (when xi is configured as an external clock input pin.) 7 sresetn connect to vddio 47 powoff open note if any input pins are left open, the current consumption may increase. therefore, it is recommended that the unused input ports and i/o ports be always fixed with ?l? or ?h? input.
fedl7066-01 ML7066 8/29 list of command/event the following table shows the command/event specifications of ML7066. command is send from mcu to the ML7066. event is send from the ML7066 to mcu. command/event name type code function set_trx_state.request command 0x02 requests the rf state change set_trx_state.confirm event 0x03 reports the result of rf state change request set_channel.request command 0x04 sets the operating channel set_channel.confirm event 0x05 reports the channel setting result set_cmp_data.request command 0x06 sets the preamble or start-of-frame delimiter (sfd) pattern for generation (tx) and comparison (rx) set_cmp_data.confirm event 0x07 reports the preamble/sfd pattern setting result set_rssi_setting.request command 0x08 sets the carrier detect condition set_rssi_seeting.confirm event 0x09 reports the carrier detect condition setting result set_tx_pow.request command 0x0a sets the transmitting power set_tx_pow.confirm event 0x0b reports the transmitting power setting result set_timer.request command 0x0c sets the intermitting operation timing set_timer.confirm event 0x0d reports the intermittent operation setting result set_pll_fit.request command 0x0e adjusts the operating channel center frequency set_pll_fit.confirm event 0x0f reports the result of frequency adjustment request set_test.request command 0x10 sets the test pattern set_test.confirm event 0x11 reports the result of test pattern setting results set_clk.request command 0x12 requests the sleep mode operation and powoff pin polarity change. set_clk.confirm event 0x13 reports the result of sleep and powoff pin polarity request set_reset.request command 0x14 request the reset operation set_reset.confirm event 0x15 reports the result of reset request set_confirm.request command 0x16 requests the interrupt masking set_confirm.confirm event 0x17 reports the interrupt mask requests set_int.request command 0x18 requests the .confirm event masking set_int.confirm event 0x19 reports the result of .confirm event mask requests set_spd.request command 0x18 sets the data rate set_spd.confirm event 0x19 reports the data rate setting request set_cmp_duration.request command 0x0e sets the comparing receive data period set_cmp_duration.confirm event 0x0f reports the comparing period setting result rx_data.indication event 0x20 notices existing receive data rssi.indication event 0x21 notices rssi result get_trx_state.request command 0x22 reads the rf state report get_trx_state.confirm event 0x23 reports the current rf state get_channel.request command 0x24 reads the channel setting get_channel.confirm event 0x25 reports the setting operation channel(s) get_cmp_data.request command 0x26 reads the setting of the preamble or sfd pattern get_cmp_data.confirm event 0x27 reports the setting pattern of preamble or sfd get_rssi_setting.request command 0x28 reads the carrier detect setting or current rssi get_rssi_seeting.confirm event 0x29 reports the carrier detect setting or current rssi get_tx_pow.request command 0x2a reads the transmitting power setting get_tx_pow.confirm event 0x2b reports the setting value of transmitting power get_timer.request command 0x2c reads the intermitting operation timing get_timer.confirm event 0x2d reports the setting value of intermittent operation get_pll_fit.request command 0x2e reads the pll adjust value get_pll_fit.confirm event 0x2f reports the setting value for pll adjustment
fedl7066-01 ML7066 9/29 command/event name type code function get_test.request command 0x30 reads the test pattern setting get_test.confirm event 0x31 reports the setting of test pattern get_clk.request command 0x32 reads the powoff pin polarity setting get_clk.confirm event 0x33 reports the setting polarity of powoff pin get_int.request command 0x34 reads the .confirm event mask setting get_int.confirm event 0x35 reports the setting of .confirm event mask get_confirm.request command 0x36 reads the interrupt mask setting get_confirm.confirm event 0x37 reports the setting of interrupt mask int.indication event 0x38 notices interrupt occurs get_spd.request command 0x3a reads the data rate get_spd.confirm event 0x3b reports the data rate setting get_cmp_duration.request command 0x0e reads the comparing period setting get_cmp_duration.confirm event 0x0f reports the setting value of comparing period get_errr_counter.request 0x3e reads the receiving error status of operating channels get_err_counter.confirm 0x3f reports the receiving data status of operating channels list of confirm code function note 0x05 invalid_parameter invalid_parameter 0x06 rx_on rx_on request when in rx_on state 0x07 success request accepted 0x08 trx_off trx_off request when in trx_off state 0x09 tx_on tx_on request when in tx_on state 0x0a unspoorted_sttribute data overrun or shortage
fedl7066-01 ML7066 10/29 ML7066 state diagram the following igure shows the state transition time and the consumption current from power-on to each power state (sleep, idle, rx, tx) . curren t (ma ) 29.500 note 1) or shorter transmit data output time + 0.2(msec) 0.2(ms) or shorter transmit data output time + 0.4(msec ) or shorter 15.500 3.0(msec) or shorter 2.4(msec) or short e note 2) receive data output time + 0.2(msec) 2.000 or 0.2(msec) or shorter 1.0(msec) or shorter 9.0(msec) or shorter 0.004 time 10.0(msec) or shorter note 1: for the trx_off instruction, the idle state comes 0.2ms after the data transmission from ML7066 is completed. for the force_trx_off instruction, it comes 0.2ms after the instruction is received. note 2: for the trx_off instruction, the idle state comes 0.2ms after the time when the unreceived data from ML7066 reduces to the last one byte. for the force trx off instruction it comes 0 2ms after the instruction is received sleep off rx tx idle receiver data outputtime +
fedl7066-01 ML7066 11/29 notes on operation this section describes the notes on using the ML7066. 1) initial settings initial settings are required for optimization of the rf characteristics. perform the following ML7066 initial settings after reset. ML7066 initial settings no. direction t yp e command data sci format 1 ML7066 mcu confirm 0x15 0x07 sdo: 0c 02 15 07 2 mcu ML7066 re q uest 0x5f 0x8888 sdi: 08 03 5f 88 88 3 mcu ML7066 re q uest 0x42 0x2111 sdi: 08 03 42 11 21 4 mcu ML7066 re q uest 0x40 0xb587 sdi: 08 03 40 87 b5 5 mcu ML7066 re q uest 0x41 0x82e9 sdi: 08 03 41 e9 82 6 mcu ML7066 re q uest 0x47 0x0883 sdi: 08 03 47 83 08 7 mcu ML7066 re q uest 0x43 0xfe01 sdi: 08 03 43 01 fe 8 mcu ML7066 re q uest 0x45 0x0020 sdi: 08 03 45 20 00 9 mcu ML7066 re q uest 0x02 0x09 sdi: 08 02 02 09 10 ML7066 mcu confirm 0x03 0x07 sdo: 0c 02 03 07 11 mcu ML7066 re q uest 0x4d 0x0040 sdi: 08 03 4d 40 00 12 set 2msec wait for mcu. 13 mcu ML7066 re q uest 0x02 0x08 sdi: 08 02 02 08 14 ML7066 mcu confirm 0x03 0x07 sdo: 0c 02 03 07 15 mcu ML7066 re q uest 0x45 0x0000 sdi: 08 03 45 00 00 16 mcu ML7066 re q uest 0x42 0x2110 sdi: 08 03 42 10 21 17 mcu ML7066 re q uest 0x5f 0x0000 sdi: 08 03 5f 00 00 2) notification from ML7066 if ML7066 state settings cause a mismatch between an instruction and an internal status, a confirmation that is not listed in t he data sheet may be notified fairly infrequently. if you receive such a confirmation, simply discard it. example) 04_ 00 (confirmation with length=0) 04_02_02_ 02 (set_trx_state.request never has the data 02) 04_05 _05_05_05_05_05 (set_rssi.indication never has length=5) 3) seal the first and second generations are distinguished by the seal. the seal of the second generation is ML7066b. note that the first generation includes the following restriction. restrictions: the timer value set in the set_timer.request command should be 15 seconds or shorter. 4) regulator the regulator in ML7066 has a built-in overcurrent protection circuit. the current control is switched between the following two levels, based on the supplied voltage. we have verified that the overcurrent protection circuit can prevent an occurred inrush current from affecting the function and lifetime of ML7066. however, it cannot prevent an inrush current of the charge in bypass capacitors or other parts at power-on alone. you should verify the protection on your implementation. for a low vreg_out output voltage (vreg_in*0.45v or lower): clamped at about 100ma. for a high vreg_out output voltage (vreg_in*0.45v or higher): clamped at about 500ma.
fedl7066-01 ML7066 12/29 5) fractional spurious ML7066 maintains the accuracy of the rf clock frequency by fine-tuning the pll oscillation frequency, which helps lower the component cost for generating the master clock. the fractiona l-n pll type is used to realize the fine tuning of the pll oscillation frequency. we found that this pll type could cause the fractional spurious depending on the combination of the reference clock, integer dividing ratio, and fractional dividing ratio. so, depending on the combination of the used frequencies (channels), a false detection of the rssi value can occur. the following matrixes show the channel combinations with a possible false detection. 426mhz band channel false detection matrix z symbol indicates the combination of the transmission and reception channels by the normal setting. symbol indicates the channel combination with a possible false detection. 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566 1 426.0250 2 426.0375 3 426.0500 4 426.0625 5 426.0750 6 426.0875 7 426.1000 8 426.1125 9 426.1250 10 426.1375 11 426.1500 12 426.1625 13 426.1750 14 426.1875 15 426.2000 16 426.2125 17 426.2250 18 426.2375 19 426.2500 20 426.2625 21 426.2750 22 426.2875 23 426.3000 24 426.3125 25 426.3250 26 426.3375 27 426.3500 28 426.3625 29 426.3750 30 426.3875 31 426.4000 32 426.4125 33 426.4250 34 426.4375 35 426.4500 36 426.4625 37 426.4750 38 426.4875 39 426.5000 40 426.5125 41 426.5250 42 426.5375 43 426.5500 44 426.5625 45 426.5750 46 426.5875 47 426.6000 48 426.6125 49 426.6250 50 426.6375 51 426.6500 52 426.6625 53 426.6750 54 426.6875 55 426.7000 56 426.7125 57 426.7250 58 426.7375 59 426.7500 60 426.7625 61 426.7750 62 426.7875 63 426.8000 64 426.8125 65 426.8250 66 426.8375 rx ch rx freq. (mhz) signal frequency
fedl7066-01 ML7066 13/29 429mhz band channel false detection matrix z symbol indicates the combination of the transmission and reception channels by the normal setting. symbol indicates the channel combination with a possible false detection. 1 2 3 4 5 6 7 8 910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061 1 429.1750 2 429.1875 3 429.2000 4 429.2125 5 429.2250 6 429.2375 7 429.2500 8 429.2625 9 429.2750 10 429.2875 11 429.3000 12 429.3125 13 429.3250 14 429.3375 15 429.3500 16 429.3625 17 429.3750 18 429.3875 19 429.4000 20 429.4125 21 429.4250 22 429.4375 23 429.4500 24 429.4625 25 429.4750 26 429.4875 27 429.5000 28 429.5125 29 429.5250 30 429.5375 31 429.5500 32 429.5625 33 429.5750 34 429.5875 35 429.6000 36 429.6125 37 429.6250 38 429.6375 39 429.6500 40 429.6625 41 429.6750 42 429.6875 43 429.7000 44 429.7125 45 429.7250 46 429.7375 47 429.7500 48 429.7625 49 429.7750 50 429.7875 51 429.8000 52 429.8125 53 429.8250 54 429.8375 55 429.8500 56 429.8625 57 429.8750 58 429.8875 59 429.9000 60 429.9125 61 429.9250 rx ch rx freq. (mhz) signal frequency
fedl7066-01 ML7066 14/29 electrical characteristics absolute maximum ratings item symbol condition rating unit power supply voltage (i/o) (*1) v ddio -0.3 +4.6 v power supply voltage (rf) (*2) v dd_rf -0.3 +3.6 v regulator input voltage v regin -0.3 v ddio +0.3 v digital input voltage v din -0.3 v ddio +0.3 v rf input voltage v rfin -0.3 v dd_rf +0.3 v analog input voltage v ain -0.3 v ddio +0.3 v regulator output voltage v regout -0.3 v dd_rf +0.3 v digital output voltage v do ta=+25c -0.3 v ddio +0.3 v rf output voltage v rfo vss=0v -0.3 v dd_rf +0.3 v analog output voltage v ao -0.3 v ddio +0.3 v digital input current i di -10 +10 ma rf input current i rf -2 +2 ma analog input current i ai -2 +2 ma digital output current i do -10 +10 ma rf output current i rfo -2 +2 ma analog output current i ao -2 +2 ma power dissipation p d ta=+25c 660 mw storage temperature t stg ? -55 +150 c *1: vddio pin *2: rf power supply pins: vdd_rf, vdd_mix, vdd_if, vdd_vco, vdd_cp, and vdd_pll pins
fedl7066-01 ML7066 15/29 recommneded operation conditions item symbol condition min. typ. max. unit power supply voltage (i/o) v ddio vddio pin (*3) 2.1 3.0 3.6 v power supply voltage (rf) v dd_rf (*2) (*4) rx 1.95 2.1 2.3 v (*2) (*4) tx 1.92 2.1 2.3 v regulator input voltage v regin vreg_in pin (*3) 2.1 3.0 3.6 v operating temperature t a ? -25 +25 +65 digital input rise time t ir digital input pins (*5) ? ? 20 ns digital input fall time t if digital input pins (*5) ? ? 20 ns digital output load c dl all digital output pins ? ? 20 pf master clock f mck xi pin (*20) -4ppm 19.2 +4ppm mhz master clock duty ratio d mck xi pin 45 50 55 % sub clock f extclk extclk pin (*21) -80ppm 32.768 +80ppm khz sub clock duty ratio d extclk extclk pin 40 50 60 % sci clock input frequency f sclk sclk pin 0.1 2 8 mhz sci clock input duty ratio d sclk sclk pin 45 50 55 % rf channel frequency1 f rf1 rf_out pin, rf_in pin 12.5khz interval 426.0250 ? 426.8375 mhz rf channel frequency2 f rf2 rf_out pin, rf_in pin 12.5khz interval 429.1750 ? 429.9250 mhz *3: v ddio =v regin *4: the vreg_out pin should be connected to each rf power supply pin. *5: applies to the pins that are indicated as i, i s , i u in the i/o column in the pin descriptions section. *20: the input clock frequency deviation is shown in the following table. *21: reference value. the frequency accuracy of the sub clock only affects timers, and does not matter for the transmit/receive operation. table:example of input clock frequency and receive characteristics reference clock frequency accuracy 21.4mhz quartz filter (bpf) characteristics 455khz ceramic filter (bpf) characteristics 4ppm 10ppm 20ppm 40ppm 60ppm 6khz 6khz 6khz 6khz 6khz 6.0khz 7.5khz 7.5khz 7.5khz 7.5khz you can use the pll frequency adjustment function provided in this lsi to support a reference clock frequency with an accuracy worse than 4ppm. when the accuracy of the reference clock frequency is worse than 4ppm, you can adjust it to ensure the requi red frequency accuracy by the pll frequency adjustment function. in terms of the receive characteristics, the bandwidth of the external filter s hould be wide as shown in this table if the accuracy of the source reference clock frequency is worse than 4ppm, which degrades the c/i characteristics. in this table, the reference clock frequency accuracy includes the center frequency and the temperature variation. the temperature variation of the reference clock frequency is uniformly assumed to be 20ppm.
fedl7066-01 ML7066 16/29 current consumption specifications (operation power supply voltage: v ddio =v regin =2.1v - 3.6v, ta=-25 - +65c) item symbol condition min. typ. (*7) max. unit i dds total-stop state ? 0.7 ? a i dd1 sleep state ? 4 ? a i dd3 idle state ? 2 ? ma i dd4 receiving state (*8) ? 15.5 ? ma current consumption (*6) i dd5 transmitting state (*8) ? 29.5 ? ma *6: the current consumption is the total current of the rf power supply pins (vdd_rf, vdd_mix, vdd_if, vdd_vco, vdd_cp, and vdd_pll pins) and the digital power supply pins (vddio and vreg_in pins). *7: the ?typ.? condition is v ddio = v regin =3.0v, 25c. *8: the value applies to the following conditions (a higher value may occur depending on the mcu operation): sci interface clock is 2mhz; data transfer rate is 4800bps.
fedl7066-01 ML7066 17/29 dc common characteristics (operation power supply voltage: v ddio =v regin =2.1v - 3.6v, ta=-25 - +65c) item symbol condition min. typ. max. unit v ih1 (*9)(*10)(*11) xi pin excluded v ddio x 0.75 ? v ddio v "h" level input voltage v ih2 xi pin v regcore x 0.9 ? v regcore v v il1 (*9)(*10)(*11) xi pin excluded 0 ? v ddio x 0.1 v "l" level input voltage v il2 xi pin 0 ? v regcore x 0.25 v schmitt trigger "h" level judgment threshold v t+ (*10) ? 1.2 1.8 v schmitt trigger "l" level judgment threshold v t- (*10) 0.4 0.8 ? v i ih1 vih= v ddio (*9)(*10)(*11) -2 ? 2 a i ih2 vih= v regout2 (*19) -2 ? 2.3 a i il1 vil=0v (*9)(*10) -2 ? 2 a i il2 vil=0v (*11) -200 -25 -5 a input leakage current i il3 vil=0v (*19) -2.3 ? 2 a v oh1 ioh=-100a (*13) v ddio - 0.2 ? v ddio v ioh=-4ma (v ddio=2.7 3.6v ) (*13) v ddio x 0.8 ? v ddio v v oh2 ioh=-4ma (v ddio=2.1 2.7v ) (*13) v ddio x 0.7 ? v ddio v "h" level output voltage v oh3 ioh=-100a (*18) 1.65 ? 2.35 v v ol1 iol=100a (*13) 0 ? 0.2 v v ol2 iol=4ma (*13) 0 ? v ddio x 0.2 v "l" level output voltage v ol3 ioh=-100a (*18) 0 ? 0.45 v v regout1 when vreg_core pin is sleeping (i regout1 =5a) 1.2 1.7 2.2 v v regout2 when vreg_core pin is idling, transmitting, and receiving (i regout2 =5ma) 1.95 2.2 2.3 v regulator output voltage v regout3 when vreg_out pin is transmitting and receiving 1.95 2.2 2.3 v c in input pin (*9)(*10)(*11) ? 6 ? pf c out output pin (*13) ? 9 ? pf c rfi rf input pin (*14) ? 9 ? pf c rfo rf output pin (*15) ? 9 ? pf c ai analog input pin (*16) ? 9 ? pf input capacitance c ao analog output pin (*17) ? 9 ? pf (*9) applies to the pins indicated as i in the i/o column in the pin descriptions section. *10: applies to the pins indicated as i s in the i/o column in the ?pin descriptions? section. *11: applies to the pins that are indicated as i u in the i/o column in the pin descriptions section. *13: applies to the pins that are indicated as o in the i/o column in the pin descriptions section, except for the xo pin. *14: applies to the pins that are indicated as i rf in the i/o column in the pin descriptions section. *15: applies to the pins that are indicated as o rf in the i/o column in the pin descriptions section.
fedl7066-01 ML7066 18/29 *16: applies to the pins that are indicated as i a in the i/o column in the pin descriptions section. *17: applies to the pins that are indicated as o a in the i/o column in the pin descriptions section. *18: xo pin. *19: xi pin.
fedl7066-01 ML7066 19/29 rf characteristics data rate : 1200/2400/4800 bps modulation method : binary fsk channel interval : 12.5khz frequency range : 426.0250mhz 426.8375 mhz : 429.1750mhz 429.9250 mhz power supply voltage (rf) : 1.95v - 2.35v (supplied from vreg_out) operating temperature : -25c 65c item condition min. typ. max. unit at 10mw mode 5 10 12 mw transmitting power at 1mw mode 0.5 1 1.2 mw transmit adjacent channel leakage rbw=4.25khz ? ? 40 dbc occupied bandwidth 99% 4 ? 8.5 khz frequency deviation 2 ? ? khz transmit spurious emissions ? ? 2.5 w ber<10 -2 fdev:1.5khz at 2400bps ? ? -113 dbm receiver sensitivity ber<10 -6 fdev::1.5khz at 2400bps ? ? -107 dbm maximum input level ber<10 -6 fdev::1.5khz at 2400bps 0 ? ? dbm receiver spurious response desired signal : reference sensitivity + 3db interfering signal: cw ber<1% 40 ? ? db receiver c/i adjacent interference 12.5khz offset desired signal: reference sensitivity + 3db interfering signal: modulation wave ber<1% 30 ? ? db receiver c/i alternate interference 25.0khzoffset desired signal: reference sensitivity + 3db interfering signal: modulation wave ber<1% 30 ? ? db receiver intermodulation characteristics desired signal: reference sensitivity + 3db interfering signal: cw adjacent channel and second adjacent channel. ber<1% 40 - - db receiver spurious emissions ? ? 4 nw rssi dynamic range 40 ? ? db rssi minimum sensitive level ? ? -105 dbm state transition time: transmitting/receiving or receiving/transmitting ? ? 1 msec (notes) in the manchester encoding mode, the transmission rates of the baseband (dio) and on the radio circuit (antenna end) are 600/1200/2400bps and 1200/2400/4800bps respectively. these rf characteristics shall be measured using the antenna terminal on an application circuit.
fedl7066-01 ML7066 20/29 synchronous communication interface (sci) characteristics (operation power supply voltage: 2.1v - 3.6v, ta=?25 - +65c) item symbol condition min. typ. max. unit sclk clock frequency f sclk except suspend 0.1 2 8 mhz scen input setup time t cesu 125 ? ? ns scen input hold time t ceh 125 ? ? ns sclk "h" pulse width t wckh 50 ? ? ns sclk "l" pulse width t wckl 50 ? ? ns sdin input setup time t disu 5 ? ? ns sdin input hold time t dih 15 ? ? ns t ceen0 positive clock 0 ? 40 ns scen output enable time t ceen1 negative clock 0 ? 20 ns scen assertion interval t ceitvl 1 ? ? us scen output disable time t cedis ? ? 25 ns t ckod ? ? 100 ns sclk output delay time t ckodf ? ? 40 ns sdo output hold time t doh load capacita nce c l = 50pf 50 ? ? ns (notes) all the timings are measured at the 20% and 80% levels of v ddio . measurement points all the following measurement points are equivalent to the above ones. when sclk is a positive clock measurem ent points 0.8v ddio 0.2v ddio 0.8v ddio 0.2v ddio scen sclk sdo sdin msb in bits6-1 lsb in t ceen0 f sclk t wckh t disu t wckl msb out bits6-1 lsb out (**) t ceh t cedis t doh t ckod t dih t doh t cesu
fedl7066-01 ML7066 21/29 when sclk is a negative clock (notes) the sint pin signal occurs at the timing independent of the signals of other clock synchronous serial interface related pins. the above diagrams show the case of input/output from the msb. it can be changed to input/output from the lsb through the mode pin setting. **: although the output value is not specified, msb data is output in the case of input/output from the msb indicated above. for input/output from the lsb, lsb data is output. scen sclk sdo sdin msb in bits6-1 lsb in t ceen1 t wckh msb out bits6-1 lsb out (**) t ceh t cedis t ckod t doh t wckl f sclk t ckodf t disu t dih t cesu scen t ceitvl
fedl7066-01 ML7066 22/29 transmit/receive data interface characteristics (operation power supply voltage: 2.1v - 3.6v, ta=-25 - +65c) item symbol condition min. typ. max. unit dio input setup time t disu at transmission 20 ? ? ns dio input hold time t dih at transmission 20 ? ? ns dclk output delay time t dckod at reception ? ? 40 ns dio output hold time t doh at reception load capacitance cl= 50pf 15 ? ? ns (notes) all the timings are measured at the 20% and 80% levels of v ddio . the dclk clock frequency f dclk is 600hz / 1200hz / 2400hz / 4800hz. reset characteristics (operation power supply voltage: 2.1v - 3.6v, ta=?25 - +65c) item symbol condition min. typ. max. unit resetn delay time (at power on) t rdl after all power supply pins are powered on 1 ? ? ms sresetn pulse time t rpls resetn=1 200 ? ? ns sresetn delay time (when operating) t rdop 1 ? ? ms resetn-sresetn setup time (when operating) t rsu 10 ? ? ns (notes) all the timings are measured at the 20% and 80% levels of v ddio . vdd vdd voltage level gnd level resetn sresetn t rdo t rdl t rpl t rsu dcl dio (at reception) dio (at transmission) valid valid valid valid valid t dckod t doh f dclk t dis t di valid t dckod f dclk
fedl7066-01 ML7066 23/29 power on and power down characteristics (operation power supply voltage: 2.1v - 3.6v, ta=?25 - +65c) item symbol condition min. typ. max. unit power-on time difference t pwon at power on between vddio - vreg_in pins ? 1 5 ms power-off time difference t pwoff at power off between vddio - vreg_in pins ? 1 5 ms (notes) no specification for the power-on order. however, each reset time after power on regulated by the resetn pin must be satisfied. timings are measured at the 20% and 80% levels of the minimum value of the power supply voltage of each power supply pin. regulator characteristics (operation power supply voltage: 2.1v - 3.6v, ta=?25 - +65c) item symbol condition min. typ. max. unit regulator power-on output response time t regon at power on vreg_out pin ? 5 10 s regulator power-off output response time t regoff at power off vreg_out pin ? 5 10 s regulator voltage input time t regin ? 5 - - ms (notes) t regon is the time from when the vreg_in pin reaches 2.2v to when the 2.1v voltage is output from the vreg_out pin at power-on. t regoff is the time from when the vreg_in pin reaches 2.2v to when the output level of the vreg_out pin begins falling at power-off. any required voltage output from the regulator should not be used after this time elapsed. t regin is the rise time (0v vdd level) of the voltage applied to the vreg_in pin at power-on.
fedl7066-01 ML7066 24/29 application circuit the following shows the typical application circuit. this circuit may vary depending on the shipment time or other factor. this this circuit and componet list are used for ml066 evaluation board. lapis semiconductor recommended that choosing and finalize the best component valuse by evaluationg on the target board. ML7066 evaluation board circuit
fedl7066-01 ML7066 25/29 component list of ml 7066 evaluation board parts no. type no. vendors remarks ic1 ML7066 lapis semiconductor ic2 pd5710tk nec cmos spdt sw saw1 nsva398 japan radio 426mhz band saw filter nsva399 429mhz band saw filter mcf1 21412ad daishinku quartz filter 21.4mhz cf1 cfukg455kf4a-r0 murata manufacturing ceramic filter 455khz x1 dsx530ga daishinku crystal oscillator 19.2mhz c1 1000pf murata manufacturing grm1882 or equivalent c2 1000pf murata manufacturing grm1882 or equivalent c3 4pf murata manufacturing grm1882 or equivalent c4 4pf murata manufacturing grm1882 or equivalent c5 1000pf murata manufacturing grm1882 or equivalent c6 5pf murata manufacturing grm1882 or equivalent c7 1.5pf murata manufacturing grm1884 or equivalent c8 7pf murata manufacturing grm1882 or equivalent c9 100pf murata manufacturing grm1882 or equivalent c10 1000pf murata manufacturing grm1882 or equivalent c11 1000pf murata manufacturing grm1882 or equivalent c12 1000pf murata manufacturing grm1882 or equivalent c13 1000pf murata manufacturing grm1882 or equivalent c14 15pf murata manufacturing grm1882 or equivalent c15 1000pf murata manufacturing grm1882 or equivalent c16 0.1f murata manufacturing grm1882 or equivalent c17 15pf murata manufacturing grm1882 or equivalent c18 15pf murata manufacturing grm1882 or equivalent c19 3300pf murata manufacturing grm1882 or equivalent c20 10f nec e/sv line-up or equivalent c21 4.7f nec e/sv line-up or equivalent c22 10pf murata manufacturing grm1882 or equivalent c23 1000pf murata manufacturing grm1882 or equivalent c24 10pf murata manufacturing grm1882 or equivalent c25 1000pf murata manufacturing grm1882 or equivalent c26 10f murata manufacturing grm188 or equivalent c27 10pf murata manufacturing grm1882 or equivalent c28 1000pf murata manufacturing grm1882 or equivalent c29 1f murata manufacturing grm1882 or equivalent c30 1f murata manufacturing grm1882 or equivalent c31 10f nec e/sv line-up or equivalent c32 1f murata manufacturing grm1882 or equivalent c33 10f nec e/sv line-up or equivalent c34 1000pf murata manufacturing grm1882 or equivalent c35 1000pf murata manufacturing grm1882 or equivalent l1 27nh murata manufacturing lqg18 or equivalent l2 15nh murata manufacturing lqg18 or equivalent l3 6.2nh murata manufacturing lqw18an6n2d00 l4 3.9nh murata manufacturing lqw18an3n9d10 l5 18nh murata manufacturing lqg18 or equivalent l6 18nh murata manufacturing lqg18 or equivalent l7 15nh murata manufacturing lqw18an15nj10 r1 2k ? koa rk73b 1j or equivalent r2 2k ? koa rk73b 1j or equivalent r3 1.5k ? koa rk73b 1j or equivalent r4 1.5k ? koa rk73b 1j or equivalent r5 16k ? koa rk73b 1j or equivalent r6 200 ? koa rk73b 1j or equivalent r7 10k ? koa rk73b 1j or equivalent r8 10 ? koa rk73b 1j or equivalent r9 47k ? koa rk73b 1j or equivalent r10 (* 1) 10k ? koa rk73b 1j or equivalent (* 1): this resistor can be inserted anywhere in the connected power line, but mandatory. in some past cases, ML7066 could not start up successfully without this resistor.
fedl7066-01 ML7066 26/29 package information recommended pcb layout reference diagram recommended land pattern [unit: mm] when designing the land pattern of the mounting board, you should give due consideration to ease of mounting, reliability of connection, wiring, and no solder bridging. the optimal design of the land pattern depends on the board material, solder type, thickness, and soldering method. this material shall be used for reference only when designing the land pattern.
fedl7066-01 ML7066 27/29 package dimensions 48 pin vqfn notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl7066-01 ML7066 28/29 revision history page document no. date previous edition current edition description fedl7066-01 apr.28, 2011 ? ? edition 1 note any editorial changes are not listed up.
fedl7066-01 ML7066 29/29 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refe r to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be us ed with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, co mmunication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation eq uipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intend ed to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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